This invention relates to the controlled growth of atomically-flat crystalline surfaces and crystal films for application to the fabrication of semiconductor devices. The invention is particularly applicable to the production of crystals (herein used to include crystal films) of silicon carbide, aluminum nitride, gallium nitride, and other compounds. A primary aspect of the invention is related to silicon carbide (SiC) and the nitrides (e.g., AlN and GaN) of the Group III elements; however, the invention has much broader applications and can be used for other compounds. For example, films of ternary and quarternary compounds (and higher order compounds) of the III-V elements (e.g., GaAlN) could be grown.
The invention is also particularly applicable to growing atomically-flat surfaces. The ability to prepare device-sized regions of atomically-flat, or nearly atomically-flat, regions on a semiconductor crystal leads to improved performance and reliability in devices such as Metal Insulator Semiconductor Field Effect Transistor (MISFET) devices known in the art. In MISFET-based transistor devices, the electrical potential of the gate influences the density of carriers (either electrons or holes) in the underlying channel region between the source and drain contacts of the MISFET, thereby modulating source-to-drain current flow. The insulator properties and thickness are chosen so as to prevent current flow of mobile carriers between the channel and the gate, yet enable the electrical potential of the gate to affect the electrical potential, and therefore the number of carriers in the source-to-drain channel, which, in turn, modulates the source-to-drain current flow.
In general, MISFET's can be divided into two sub-categories: 1) buried channel MISFET's in which majority carrier current flow takes place well below the insulator-semiconductor interface (approximately a Debeye Length (known in the art) into the semiconductor below the semiconductor-insulator interface), and 2) surface channel MISFET's where the vast majority of transistor current flow takes place just on the semiconductor side of the insulator-semiconductor interface. The very thin, high density layer of mobile carriers localized at the insulator-semiconductor interface in a surface-channel MISFET is often referred to as an "inversion layer" or "2 Dimensional Electron Gas layer." The most commonly employed sub-category of surface-channel MISFET devices is the inversion-channel MOSFET (Metal Oxide SiO.sub.2 ! Semiconductor Field Effect Transistor) which is the basic building block device for the vast majority of semiconductor integrated circuits on the market today. Another useful sub-category of surface-channel MISFET is known as the High Electron Mobility Transistor, or HEMT. Instead of using a true dielectric insulator such as Sio.sub.2, the HEMT structure often employs a wider-bandgap semiconductor to serve as the "insulator" that resides between the gate and a narrower-bandgap semiconductor channel.
It is well-known to those skilled in the art that the electrical performance and reliability of surface channel MISFET's are greatly impacted by. the quality of the insulator-semiconductor interface, especially its flatness dimension. In order to maximize transistor gain and current-carrying capability, it is desired that the effective mobility of carriers in the surface channel (i.e., inversion layer) be maximized. Spacial non-uniformities in the insulator-semiconductor interface (i.e., interface non-flatness) have repeatedly been shown to hinder the acceleration and flow of carriers in surface-channel MISFET inversion layers leading to reduced effective channel carrier mobilities which, in turn, cause decreased transistor gain and reduced current carrying capability. Furthermore, it is also well-known and well-documented that interface non-flatness (more commonly referred to as interface roughness) also impacts long-term reliability of MISFET's, particularly in MOSFET devices where high electric fields or high temperatures are encountered.
From a structural point of view, the ideal insulator-semiconductor interface in any MISFET structure is one that is atomically-flat along the interface, and is atomically abrupt across the interface in that the last monolayer of 100% semiconductor is immediately followed by the first monolayer of 100% insulator (i.e., no transitional monolayer of 50% insulator 50% semiconductor for example). The term "atomically-flat" is known in the art and is generally referred to herein as meaning a surface that is totally without any atomic-scale or macro-scale steps over an area defined by selected boundaries that may be created by grooves in a manner to be further described herein with reference to FIG. 4. The present invention, as will be described hereinafter, provides methodologies for obtaining large areas of atomically-flat surfaces, as well as atomically abrupt defect-free interfaces between two materials with different electrical properties, both of which could be employed in the fabrication of improved structurally ideal MISFET devices.
The formation of atomically-flat surfaces for a MISFET device in and of itself could in many cases be used to improve MISFET performance. More particularly, any insulator layer placed on top of the semiconductor as part of a MISFET process, regardless of deposition or thermal growth method, would likely have better (though not necessarily atomically-flat) interface roughness properties if starting from a relatively flat substrate prepared in accordance with the present invention, as to be described, rather than starting from a prior art substrate. In the case of inversion-channel MOSFET's superior smoothness is likely to be present after a thermal oxidation starting from an atomically-flat surface, prepared according to the present invention, which could improve effective inversion channel carrier mobilities, MOSFET gain and peak current, and improve MOSFET oxide reliability under real-world high-field and/or high-temperature operating conditions. While the above discussion has been directed primarily to surface-channel MISFET devices, the principles of this invention could be used to improve any structure that is impacted by the atomically flatness and/or atomically abruptness of a material junction, including homojunction semiconductor devices.
Semiconductor devices, including MISFET devices all related to the present invention, are used in a wide variety of electronic applications. Semiconductor devices include diodes, transistors, integrated circuits, sensors, and opto-electronic devices such as light-emitting diodes and diode lasers. Various semiconductor devices using silicon or compound semiconductors such as gallium arsenide (GaAs) and gallium phosphide (GaP) are commonly used. In order to fabricate semiconductor devices, it is necessary to be able to grow high-quality, low-defect-density single-crystal films with controlled impurity incorporation while possessing good surface morphology. The substrate upon which the film is grown should also be a high-quality, low-defect-density single crystal. In recent years, there has been an increasing interest in research on wide-bandgap semiconductors for use in high temperature, high power, high frequency, and/or high radiation operating conditions under which silicon and conventional III-V semiconductors cannot adequately function. Particular research emphasis has been placed on SiC, AlN, and GaN. It is believed by many experts that SiC will have advantages for high power applications because of its high breakdown electric field, high thermal conductivity, and GaN will have advantages for opto-electronic applications because of its wide direct bandgap. The recent development of commercial very bright blue GaN light emitting diodes (LED's) has spurred the world wide development efforts to produce blue and/or ultraviolet (uv) GaN laser diodes particularly suited for increased data capacity in digital optical storage media such as compact disc (CD) players.
Silicon carbide has characteristics that make it highly advantageous for applications involving high temperature, high power, high frequency, and/or high radiation operating conditions. Such characteristics include a wide energy bandgap of 2.2 to 3.3 electron volts (depending on polytype), a high thermal conductivity, a high breakdown electric field, a high saturated electron drift velocity, and high dissociation temperature. Furthermore, silicon carbide is thermally, chemically and mechanically stable and has a great resistance to radiation damage. A variety of silicon carbide semiconductor devices have been fabricated and operated to temperatures exceeding 600.degree. C.
Several properties of SiC make crystal growth difficult. First, Sic does not melt at reasonable pressures and it sublimes at temperatures above 1800.degree. C. Second, Sic grows in many different crystal structures, called polytypes. Since melt-growth techniques cannot be applied to SiC, two techniques have been developed to grow SiC crystals. The first technique is known as chemical vapor deposition (CVD) in which reacting gases are introduced into a growth chamber to form SiC crystals on an appropriate heated substrate. A second technique for growing SiC crystals is generally referred to as the sublimation process (or modified sublimation process). In the sublimation technique, some type of solid SiC material other than the desired single crystal in a particular polytype is used as a starting material and heated until the solid SiC sublimes. The vaporized material is then condensed onto a seed crystal to produce the desired bulk single crystal. The sublimation process is still far from perfect because it produces many defects in the bulk crystal. A very serious defect is a tubular void (known as a micropipe), on the order of a micrometer in diameter, which propagates in the direction of growth. The density of micropipes in state-of-the-art commercial crystals is on the order of 100 cm.sup.-2 and these are known to cause undesired premature electrical breakdown in pn junctions. Line dislocations also are produced in these bulk crystals at density of about 10.sup.4 cm.sup.-2 and these dislocations are believed to contribute to undesirable leakage currents in reversed-biased pn junctions.
Silicon carbide crystals exist in hexagonal, rhombohedral and cubic crystal structures. Generally, the cubic structure, with the zincblende structure, is referred to as .beta.-siC or 3C-SiC, whereas numerous polytypes of the hexagonal and rhombohedral structures are collectively referred to as .alpha.-SiC. To our knowledge, only bulk (i.e., large) crystals of the .alpha. polytypes have been grown to date; the .beta. (or 3C) polytype can only be obtained as small (less than 1 cm.sup.2) blocky crystals or thick epitaxial films on small 3C substrates or crystal films grown heteroepitaxially on some other substrate. The most commonly available .alpha.-SiC polytypes are 4H-SiC and 6H-SiC; these are commercially available as polished wafers, presently up to 35 mm in diameter. Each of the SiC polytypes has its own specific advantages over the others. For example, (1) 4H-SiC has a significantly higher electron mobility compared to 6H-SiC; (2) 6H-SiC is used as a substrate for the commercial fabrication of GaN blue light-emitting diodes (LED's); and (3) 3C-SiC has a high electron mobility similar to that of 4H and may function over wider temperature ranges, compared to the .alpha. polytypes.
Silicon carbide polytypes are formed by the stacking of double layers of Si and C atoms. Each double layer may be situated in one of three positions, known as A, B, and C. The sequence of stacking determines the particular polytype; for example, the repeat sequence for 3C is ABCABC . . . (or ACBACB . . . ), the repeat sequence for 4H is ABACABAC . . . , and the repeat sequence for 6H is ABCACBABCACB . . . . From this it can be seen that the number in the polytype designation gives the number of double layers in the repeat sequence and the letter denotes the structure type (cubic, hexagonal, or rhombohedral). The stacking direction is designated as the crystal c-axis and is in the crystal 0001! direction; it is perpendicular to the basal plane which is the crystal (0001) plane. The {111} planes of the cubic structure are equivalent to the (0001) plane of the .alpha. polytypes. The SiC polytypes are polar in the &lt;0001&gt; directions: in one direction, the crystal face is terminated with silicon (Si) atoms; in the other direction, the crystal face is terminated with carbon (C) atoms. These two faces of the (0001) plane are known as the Si-face and C-face, respectively. As used herein, "basal plane" shall refer to either the (0001) plane for a .alpha.-sic, or the (111) plane of 3C-SiC. The term "vicinal (0001) wafer" shall be used herein for wafers whose polished surface (the growth surface) is misoriented less than 8.degree. from the basal plane. The angle of misorientation shall be referred to herein as the tilt angle. The term "homoepitaxial" shall be referred to herein as epitaxial growth, whereby the film and the substrate (wafer) are of the same polytype and material, and the term "heteroepitaxial" shall be referred to herein as epitaxial growth whereby the film is of a different polytype or material than the substrate.
As of now, to our knowledge, there is no existing method for producing large (greater than 1-inch diameter) high-quality single-crystal 3C-SiC boules. Hence, no acceptable-quality 3C-SiC wafers are available. In a prior art process, single-crystal homoepitaxial 6H-SiC films can be grown on vicinal 6H-SiC substrates with tilt angles in the range 0.1.degree. to 6.degree. in the temperature range 1400.degree. C. to 1600.degree. C. by chemical vapor deposition (CVD) if the surface is properly prepared in a manner more fully described in U.S. Pat. No. 5,248,385 which is herein incorporated by reference. In addition to homoepitaxial 6H-SiC on 6H-SiC, 3C-SiC can be heteroepitaxially grown on 6H-SiC (or other .alpha.-SiC) substrates with tilt angles less than 1.degree.. However, this generally results in 3C-SiC films which have defects known as double positioning boundaries (DPB's). The DPB's can arise because of the change in stacking sequence of the 6H-SiC wafer (i.e., ABCACB . . . ) to that of 3C-SiC (ABC . . . or ACB . . . ) at the interface between the two polytypes. The difference between the two 3C sequences is a 60.degree. rotation about the &lt;111&gt; axis. If both of these two sequences nucleate on the 6H-SiC substrate, DPB's will form at the boundary of the domains containing the two sequences.
Theories explaining epitaxial single-crystal growth are well known. Crystal growth can take place by several mechanisms. Two of these are: (1) growth can take place by the lateral growth of existing atomic-scale steps on the surface of a substrate, and (2) growth can take place by the formation of two-dimensional atomic-scale nuclei on the surface followed by lateral growth from the steps formed by the nuclei. The lateral growth from steps is sometimes referred to as "step-flow growth." In the first mechanism, growth proceeds by step flow from existing steps without the formation of any two-dimensional nuclei (i.e., without 2D nucleation). In the nucleation mechanism, the nucleus must reach a critical size in order to be stable; in other words, a potential energy barrier must be overcome in order for a stable nucleus to be formed. Contamination or defects on the substrate surface can lower the required potential energy barrier at a nucleation site. In the processes described in this invention, crystal growth proceeds by (1) step flow without 2D nucleation, or by (2) step flow with 2D nucleation. Step flow growth with 2D nucleation allows the growth of epitaxial films of any desired thickness.
A prior art process for growing 3C-SiC on 6H-SiC with reduced density of DPB's is presented in U.S. Pat. No. 5,363,800 ('800) which is herein incorporated by reference. In this improved process, the surface of a 6H-SiC substrate with a tilt angle of less than 1.degree. is divided up into an array of selected regions (herein called mesas) that are separated from one another by grooves. Each mesa acts as an independent substrate. In the process of the '800 patent, nucleation of 3C-SiC is caused to occur at the topmost atomic plane of each mesa, preferably at one corner of the mesa, and then 3C-SiC grows laterally from this point and eventually covers the whole mesa. It is assumed in this process of the '800 patent that the vicinity of the topmost plane of each mesa is atomically flat and is thus a preferred site for 3C-SiC nucleation. This prior art process of the '800 patent appears to have several disadvantages. First, it does not give any reproducible method for causing 3C-SiC to nucleate at the desired location on each mesa. Second, the 3C-SiC nucleation takes place when there are still atomic-scale steps on the mesa; these steps can act as nucleation sites for 3C-SiC if there are defects or contamination present on the surface. And finally, although the density of DPB's and associated stacking fault are greatly reduced, stacking fault density due to other causes appear to be still very high.
Using other prior art growth techniques, we have observed the nucleation of a large density of two-dimensional islands on 6H-SiC substrates in crystal growth experiments using chemical vapor deposition (CVD). In growth experiments by Kimoto and Matsunami on "well-oriented" (i.e., very small tilt angles with respect to the basal plane) Sic substrates over the temperature range 1200.degree. C. to 1600.degree. C., nucleation densities in the range 4.times.10.sup.3 to 1.times.10.sup.6 cm.sup.-2 were observed. In these same experiments, Kimoto and Matsunami observed 3C-SiC nuclei with two different rotational orientations growing on the "well-oriented" 6H-SiC substrates. The experiments of Kimoto and Matsunami are disclosed in the technical article "Nucleation and Step Motion in Chemical Vapor Deposition of SiC on 6H-SiC {0001} Faces," by T. Kimoto and H. Matsunami, published in J. Applied Physics, Vol. 76, No. 11, pp.7322-7327 (1994), and which is herein incorporated by reference.
As discussed above, 3C-SiC, to our knowledge, is not available in high-quality single-crystal wafer form; hence, the epitaxial 3C-SiC device structures must be grown heteroepitaxially on some other material. The present invention overcomes the problems of prior art in the growth of high-quality low-defect 3C-SiC films on 6H-SiC substrates.
In addition to non-availability of high-quality 3C-SiC single-crystal wafers, other wide-bandgap semiconductor compounds that are not available in single-crystal wafer form and which have great commercial potential are the nitrides of aluminum and gallium. Gallium nitride (GaN), in particular, has great potential as an optoelectronic material. Currently, commercial light-emitting diodes are being fabricated by growing GaN films on 6H-SiC or sapphire substrates. Even though these films have extremely high defect density (typically around 10.sup.10 cm.sup.-2), very bright and efficient LED's can be fabricated. Pulsed blue lasers have been fabricated from GaN; continuous blue lasers that operate for a brief time before failure have been fabricated. The present invention provides a means for reducing defects in the GaN films and hence make a practical continuous-duty GaN laser possible.
In prior art growth experiments reported by Davis et al in a technical article entitled "Initial Stages of Growth of Sic and AlN Thin Films on Vicinal and On-axis Surfaces of 6H-SiC (0001)," published in Inst. Phys. Conf. Ser. No. 142, Chapter 1, page 133 (which is herein incorporated by reference), low-defect films of 3C-SiC and 2H-AlN were grown on terraces on "on-axis" (i.e., low tilt angle) 6H-SiC substrates. The films were grown by gas-source molecular beam epitaxy (GSMBE) and had thicknesses of less than 2 nm. In other prior art experiments by the same research group and reported by Tanaka et al in a technical article entitled "Control of the Polytypes (3C, 2H) of Silicon Carbide Thin Films Deposited on Pseudomorphic Aluminum Nitride (0001) Surfaces," published in Inst. Phys. Conf. Ser. No. 142; Chapter 1, page 109 (herein incorporated by reference), 3C-SiC and 2H-SiC were grown by GSMBE on the thin films of 2H-AlN on "on-axis" 6H-SiC substrates. The C/Si ratio of the input gases determined the polytype of the SiC film: C/Si=1 yielded 3C-SiC and C/Si=5 yielded 2H-SiC. Very few defects were observed in films grown on the on-axis substrates compared to films grown on off-axis (i.e., 3.degree. tilt angle) substrates. A possible drawback with these experiments is that the results were obtained on atomic-scale terraces on the on-axis substrates. We do not have any knowledge of any method of making these atomic-scale results applicable to larger useful device-sized regions of the substrates. Also, there is no discussion by Davis et al of the impact of defects in the SiC substrates on the quality of the crystal films.
In another prior art process reported by Morlock et al., entitled "Extremely Flat Layer Surfaces in Liquid Phase Epitaxy of GaAs and Al.sub.x Ga.sub.1-x As" by U. Morlock, M. Kelsch, and E. Bauser, published in J. Crystal Growth, Vol. 87, pp.343-349 (1988), which is herein incorporated by reference, extremely flat surfaces were produced on mesas up to 1 mm.sup.2 in size on GaAs and AlGaAs substrates by a liquid phase epitaxy (LPE) process. These flat surfaces appeared as facets on the top of the mesas. Although the surfaces were extremely flat, from our understanding the surfaces actually consisted of very shallow hillocks where the center of each hillock was a dislocation that acted as a continuous source of steps. Accordingly, each mesa was covered with monomolecular steps emanating from the numerous localized step sources. The terrace width (distance between steps) varied from 0.5 to 50 .mu.m.
A disadvantage of prior art processes for the growth of SiC epilayers on SiC substrates (e.g., homoepitaxial growth of 6H-SiC on 6H-SiC) is that the step-flow growth employed in growth on "off-axis" commercial wafer can result in epilayers with large surface steps (tens of nanometers high) formed by the "step bunching" of smaller atomic-scale steps (approximately 1 nanometer high). These steps may very well hinder the development and operation of small scale devices which are of concern to the present invention.